由电子科学与工程学院主办的“电子论坛”第57期邀请到印度理工学院鲁尔基分校Brajesh Kumar Kaushik副教授，与我校师生共同探讨3d FinFET技术在解决短沟道效应时带来的新挑战，并利用模型进一步研究解决方案，加强设计者对内部器件物理机制的理解。具体安排如下，欢迎感兴趣的师生参加。
主 题：Modeling and Applications of FinFET
主讲人：Brajesh Kumar Kaushik（印度理工学院鲁尔基分校 副教授）
3-D Fin-type field effect transistors (FinFETs) have been widely adopted by industries for 22 nm and 14 nm technology nodes to address the challenges of short channel effects. The advantages of FinFET technology come with several challenges. In sub-20-nm regime, suppression of short-channel effects (SCEs) can be achieved by incorporating underlap regions. However, the difficulty in fabricating precisely controlled and well-defined doping profile necessitates the usage of undoped underlap regions. The other two inherent challenges associated with FinFETs are the higher magnitude of parasitics (due to its 3-D nature) and the fin width quantization that limits its applicability to some extent in high-performance circuits. These challenges in FinFET technology shows that there is still a lot of scope for research in this area. Hi-k spacer technologies have been proposed to address the problem of undoped underlap regions. The source/drain series resistance and parasitic fringe capacitance plays crucial role in determining the performance of dual-k spacer technology.
Brajesh Kumar Kaushik received his Doctorate of Philosophy (Ph.D.) in 2007 from Indian Institute of Technology, Roorkee, India. He joined Department of Electronics and Communication Engineering, Indian Institute of Technology, Roorkee, as Assistant Professor in December 2009; and since April 2014 he has been an Associate Professor. He has served as General Chair, Technical Chair, and Keynote Speaker of many reputed international and national conferences. Dr. Kaushik is a Senior Member of IEEE and member of many expert committees constituted by government and non-government organizations. Dr. Kaushik has been conferred with Distinguished Lecturer award of IEEE Electron Devices Society (EDS) to offer EDS Chapters with quality lectures in his research domain. His research interests are in the areas of high-speed interconnects, low-power VLSI design, memory design, carbon nanotube-based designs, organic electronics, FinFET device circuit co-design, electronic design automation (EDA), spintronics-based devices, circuits and computing, image processing, and optics & photonics based devices.
编辑：何易虹 / 审核：罗莎 / 发布者：陈伟